#define     X0_UART0_BASE              0x30000000 // 0x42020000

#define     UART0_RBR                   X0_UART0_BASE+0x0
            //b7 :b0   ,  Receive Buffer Register   ,  fifo_head
            //Note : can be accessed onlu when the DLAB bit(LCR{7]) is cleared
#define     UART0_THR                   X0_UART0_BASE+0x0
            //b7 :b0   ,  Transmit Holding Register ,  fifo_head
            //Note : can be accessed onlu when the DLAB bit(LCR{7]) is cleared

#define     UART0_DLL                   X0_UART0_BASE+0x0
            //b7 :b0   ,  Divisor latch , Low 8bit
            //Note : can be accessed onlu when the DLAB bit(LCR{7]) is set

#define     UART0_IER                   X0_UART0_BASE+0x4
            //b7       ,  Programmable THRE Interrupt Mode Enable
            //b6:b5    ,  RSVD
            //b4       ,  ELCOLR, The method for clearing the status in LSR
            //b3       ,  EDSSI, Enable/Disable the generation of Modem Status Int
            //b2       ,  ELSI, Enbale Receiver Line Status Interrupt
            //b1       ,  ETBEI, Enable Transmit Holding Register Empty Int
            //b0       ,  ERBFI, Enable Received Data Available Interrupt

#define     UART0_DLH                   X0_UART0_BASE+0x4
            //b7 :b0   ,  Divisor latch , High 8bit

#define     UART0_IIR                   X0_UART0_BASE+0x8       //RO
            //b3:b0    ,  Interrupt ID
            //b5:b4    ,  RSVD
            //b7:b6    ,  FIFOs are enabled/disabled

#define     UART0_FCR                   X0_UART0_BASE+0x8       //WO
            //b0       ,  FIFO Enable, change this bit will reset FIFO ctrl
            //b1       ,  RCVR FIFO Reset, write 0 is not allowed
            //b2       ,  XMIT FIFO Reset
            //b3       ,  DMA Mode  0:transmit   1:receive
            //b5:b4    ,  TX Empty Trigger
            //              0x0: FIFO_Empty      0x1: 2 chars in FIFO
            //              0x2: FIFO 1/4 full   0x3: FIFO 1/2 full

#define     UART0_LCR                   X0_UART0_BASE+0xc
            //b1:b0    ,  DLS,Data Length Select
            //              0x0: 5 bits/char     0x1: 6bits/char
            //              0x2: 7 bits/char     0x3: 8bits/char
            //b2       ,  STOP , Number of stop bits 
            //              0x0: 1 stop_bit      0x1: 1.5(5bits/char)/2 stop_bit
            //b3       ,  PEN, Parity Enable
            //b4       ,  EPS, Even Parity Select
            //b5       ,  SP, Stick Parity Enable  0x0:disabled
            //b6       ,  BC, Break Control Bit  0x0: disabled
            //b7       ,  DLAB, Divisor Latch Access Bit

#define     UART0_MCR                   X0_UART0_BASE+0x10

#define     UART0_LSR                   X0_UART0_BASE+0x14
            //b0       ,  Data Ready bit   0x1: data ready
            //b1       ,  Overrun error bit
            //b2       ,  PE, Parity Error bit
            //b3       ,  FE, Framing Error bit
            //b4       ,  BI, Break Interrupt bit
            //b5       ,  THRE, Transmit Holding Register Empty bit
            //b6       ,  TEMT, Transmitter Empty bit
            //b7       ,  RFE, Receiver FIFO Error bit
            //b8       ,  ADDR_RCVD , Address Received Bit

#define     UART0_MSR                   X0_UART0_BASE+0x18   //Modem Status

#define     UART0_SCR                   X0_UART0_BASE+0x1c   //Temp Storage for sw
#define     UART0_FAR                   X0_UART0_BASE+0x70

#define     UART0_USR                   X0_UART0_BASE+0x7c
            //b0       ,  UART is Busy
            //b1       ,  Transmit FIFO is Not Full  0x0:tx fifo full
            //b2       ,  Transmit FIFO is Empty  0x1:empty
            //b3       ,  RFNE, Receive FIFO not Empty  0x0:rx fifo empty
            //b4       ,  RFF , Receive FIFO Full,  0x1:full

#define     UART0_TFL                   X0_UART0_BASE+0x80
            //bx:b0    ,  Transmit FIFO Level

#define     UART0_RFL                   X0_UART0_BASE+0x84
            //bx:b0    ,  Receive FIFO Level

#define     UART0_SRR                   X0_UART0_BASE+0x88
            //b0       ,  UART Reset
            //b1       ,  RCVR FIFO Reset
            //b2       ,  XMIT FIFO Reset

#define     UART0_HTX                   X0_UART0_BASE+0xa4
            //b0       ,  HTX, 0x1: Halt Transmission enabled

#define     UART0_DMASA                 X0_UART0_BASE+0xa8
            //b0       ,  DMA Software Acknowledge

#define     UART0_TCR                   X0_UART0_BASE+0xac
            //b0       ,  RS485_EN , 0x0 : RS232 Mode 0x1 : RS485 Mode
            //b1       ,  RE_POL, 0x0: RE signal is active low
            //b2       ,  DE_POL
            //b4:b3    ,  XFER_MODE, Transfer mode

#define     UART0_PROT_LVL              X0_UART0_BASE+0xd0
            //b2:b0    ,  Protect level

#define     UART0_CPR                   X0_UART0_BASE+0xf4
            //b0       ,  


